XAUI

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XAUI

Name	Doc Version	Size	Date

XAUI v9.1 Getting Started Guide (PDF) View Document Details The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools. Was this document helpful? Yes \| No	2.1	519 KB	09/16/2009
XAUI v9.1 User Guide (PDF) View Document Details The XAUI v9.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools. Was this document helpful? Yes \| No	3.1	2.03 MB	09/16/2009
XAUI v9.1 Data Sheet (PDF) View Document Details The LogiCORE™ IP XAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system. Was this document helpful? Yes \| No	2.1	446 KB	09/16/2009

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