Device Data Sheets

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

All package files are ASCII files in zip format.

The HW-130 Programmer is a desktop, device programmer. The HW-130 Programmer supports XC1700/XC17S00/XL PROMs, XC17V00/XC17S00A PROMs, XC18V00 PROMs, XC9500/XL/XV CPLDs, and XCR3000XL CPLDs.

The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates.

The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide 3,000 usable gates.

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates.

Spartan®-II FPGA Family data sheet, including Overview, Functional Description, Specifications, and Pin-Outs.

Data Sheet for 72 macrocell 5V programmable CPLD

Data Sheet for 36 Macrocell 5V Programmable CPLD

Data Sheet for 288 Macrocell In-System Programmable CPLD

Data Sheet for 216 Macrocell 5V In-System Programmable CPLD

Features, Introduction, Detailed Functional Description, Pin Descriptions, Configuration, Configuration Timing

The Xilinx Automotive (XA) Spartan®-3E family of FPGAs is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronics applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates.

Comma-delimited ASCII text files and Excel spreadsheet maps for each package type

Comma-delimited ASCII text files and Excel footprints for each package type in the Extended Spartan®-3A Family (Spartan-3A, Spartan-3AN, and Spartan-3A DSP platforms).

Excel file to calculate DFS output jitter based on input and output clock frequencies. Applies to Spartan®-3A, Spartan-3AN, and Spartan-3A DSP platforms.

Comma-delimited ASCII text files and Excel spreadsheet maps for each package type

XA95144XL Automotive CPLD Data Sheet

XA9572XL Automotive CPLD Data Sheet

Automotive XA9526XL CPLD Data Sheet

QPro™ Virtex®-4 FPGAs are available in -10 speed grade and qualified for industrial (TJ = –40°C to +100°C), and for military (TJ = –55°C to +125°C) operational temperatures.

Spartan®-3AN FPGA Family Data Sheet, including Overview, Specifications, and Pinouts. See the Spartan-3 Generation User Guides for additional information.

Automotive data sheet for 384 macrocell CoolRunner-II CPLD

Automotive data sheet for 64 macrocell CoolRunner-II CPLD

Automotive Data Sheet for 32 macrocell CoolRunner-II CPLD

Low-power Spartan™-3L data sheet. Explains how the Spartan-3L family is different from the Spartan-3 family. Note that this family is being discontinued. For specifications and other information common to both families, see the standard Spartan-3 data sheet.

Spartan™-3E FPGA Family Data Sheet (all four modules). See the Spartan-3 Generation User Guides for additional information.

The CoolRunner™-II 64A-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 32A-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

Platform Cable USB is a high-performance download cable that attaches to user hardware for the purpose of programming or configuring Xilinx devices such as ISP Configuration PROMs, CPLDs, and FPGAs.

Complete data sheet for Platform Flash In-System Programmable Configuration PROMs. Available in 1 to 32 Megabit densities (XCF01S, XCF02S, XCF04S, XCF08P, XCF16P, and XCF32P), these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx® FPGA configuration bitstreams.

The MultiPRO Desktop Tool is a multi-function desktop programmer and configuration cable.

This document is a brief introduction to the features of the Virtex™-4 family. It contains the device summary, packaging options, and ordering information.

The XA9500XL 3.3V CPLD Automotive XA product family is targeted for leading-edge, high-performance automotive applications that require either automotive industrial (–40°C to +85°C ambient) or extended (–40°C to +105°C ambient, with Tj maximum of 125°C) temperature reconfigurable devices.

The XC9500XL 3.3V CPLD Automotive IQ product family is targeted for leading-edge, high-performance, low-voltage extended industrial (–40°C to +125°C) applications.

Introduction, Features, General Overview, DC Specifications, Spartan-IIE Product Availability, Ordering Information

The Spartan™-II 2.5V Field-Programmable Gate Array (FPGA) Automotive IQ product family gives users high-performance, abundant logic resources, and a rich feature set. The six-member family offers densities ranging from 15,000 to 200,000 system gates.

This document is a brief introduction to the features of the Virtex®-5 devices. It contains the device summary, packaging options, and ordering information.

Spartan®-3 FPGA Family Data Sheet, including Overview, Specifications, and Pinouts. See the Spartan-3 User Guides for additional information.

QPro Virtex-E Combined Data Sheet (all four modules).

The Xilinx Parallel Cable IV is a high-speed JTAG or slave-serial download cable that configures or programs all Xilinx® FPGA, CPLD, and ISP PROM devices. Connects to PC IEEE STD 1284 parallel port.

The CoolRunner™-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 384-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 128-macrocell device is designed for both high-performance and low-power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

Xilinx CoolRunner™-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3™ family in a single CPLD.

All four modules of the data sheet, plus a summary cover page compiled into a single PDF file.

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions.

Xilinx developed the System Advanced Configuration Environment (System ACE™) to address the need for a space-efficient, pre-engineered, high-density configuration solution for systems with multiple FPGAs.

The XC17S00A family of one-time programmable PROMs provide an easy-to-use, cost-effective method for storing Spartan™-II/Spartan™-IIE device configuration bitstreams.

All four modules of Spartan-IIE FPGA family data sheet in one Acrobat PDF file for easy searching.

The XC17V00 family is a 3.3V, one-time programmable PROM that can directly configure Virtex® FPGAs. The XC17V00 PROM is available in densities from one megabit (Mb) to 16 Mb.

The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns.

The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles.

Complete description and specifications for the 5V Spartan® and 3.3V Spartan-XL FPGA families.

XC9536XL 3.3V High-Performance CPLD

XC9572XL 3.3V High-Performance CPLD

XC95144XL 3.3V High-Performance CPLD

XC95288XL 3.3V High-Performance CPLD

Data Sheet for XC9536XV 36 Macrocell 2.5V CPLD.

Data Sheet for XC9572XV 72 Macrocell 2.5V CPLD.

Data Sheet for XC95144XV 144 Macrocell 2.5V CPLD

Data Sheet for XC95288XV 288 Macrocell 2.5V CPLD

Family data sheet for XC9500XV 2.5V CPLD.

All four modules of the data sheet plus a summary cover page compiled into a single PDF file.

Data sheet for one-time programmable, read-only XC17S00 and XC17S00XL PROMs designed to store configuration bitstreams for Spartan® and Spartan-XL FPGAs.

Data sheet for the XC1700E, XC1700EL, and XC1700L series Configuration PROMs.

XC18V00 series of in-system programmable configuration PROMs: Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-to-use, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.

This document provides an overview of the radiation-tolerant Virtex®-4 QPro™-V family.

This data sheet provides the DC and switching characteristics for the radiation-tolerant Virtex®-4 QPro™-V FPGAs.

CoolRunner™-II 32A マクロセル デバイスは、高性能および低消費電力アプリケーション用にデザインされいます。このことは、ハイエンド コミュニケーション装置の電力を節約し、バッテリで動作するデバイスを高速化するために有用です。低消費電力スタンバイ機能とダイナミック オペレーションによって、システム全体の信頼性が向上しています。

Virtex®-5 FPGA Aurora 64B/66B コアは、Virtex-5 FXT FPGA の Aurora プロトコルをインプリメントします。コアは、サポートされるライン レートで最大 24 個の RocketIO™ GTX トランシーバを使用できるため、662Mb/s ～ 6.25Gb/s を超える処理能力を備えた低コストで汎用のデータ チャネルを提供します。

入力および出力周波数に基づいて DFS 出力ジッタを算出するための Excel ファイルです。これは Spartan®-3A、Spartan-3AN、Spartan-3A DSP プラットフォームに適用されます。

Aurora v3.0 コアのデータシートです。

The Spartan®-3A DSP family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, high-performance DSP applications.

フィールド プログラマブル ゲート アレイ （FPGA) の Spartan®-3A DSP ファミリは、大容量、費用重視、高性能 DSP アプリケーションにおけるデザイン目標のほとんどを解決します。

Spartan®-3A FPGA Family Data Sheet, including Overview, Specifications, and Pinouts. See the Spartan-3 Generation User Guides for additional information.

This data sheet specifies the electrical characteristics of Virtex®-5Q FPGAs, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.

This document introduces the Defense-grade Virtex®-5Q FPGAs. It contains the feature list, device summary, packaging options, and ordering information.

高信頼性製品 Virtex®-5Q FPGA のデータシートです。 本書には、機能リスト、デバイス サマリ、パッケージ オプション、および注文情報が記載されています。

This data sheet describes the XC9500XL 3.3V CPLD family, including architecture, basic family device descriptions, and package options.

The CoolRunner™ XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power-sensitive applications. Each member of the XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed.

The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns.

Automotive data sheet for 128 macrocell CoolRunner™-II CPLD

All packages are ASCII files in txt format.

All package files are ASCII files in txt format.

This data sheet specifies the electrical characteristics of the Virtex®-4 Family, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.

The Xilinx® Automotive (XA) Spartan®-3 family of Field-Programmable Gate Arrays meets the needs of high-volume, cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million system gates.

パッケージ ファイルはテキスト形式の ASCII ファイルで提供されます。

Automotive data sheet for the 256-macrocell CoolRunner™-II CPLD

This overview outlines the features and product selection of the Virtex®-6 family.

This overview outlines the features and product selection of the Spartan®-6 family.

This data sheet contains the DC and switching characteristic specifications for the Virtex®-6 family.

This data sheet contains the DC and switching characteristic specifications for the Spartan®-6 family.

Spartan®-6 ファミリの特長および仕様について記載しています。

このデータシートには、Spartan®-6 ファミリの特性およびスイッチ特性が記載されています。

このデータシートには、Virtex®-6 ファミリの特性およびスイッチ特性が記載されています。

Virtex-6 ファミリの特長および仕様について記載しています。

This data sheet specifies the electrical characteristics of the Virtex®-5 family of FPGAs, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.