Application Notes

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML555 PCI/PCI Express Development Platform.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller.

This document provides a description of the CMOS output structures of the CoolRunner™ CPLDs and details some advantages of using true CMOS (rail-to-rail capable) output drivers.

This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one clock and 16 data channels). The design can be implemented in both Virtex-II™ and Virtex-II Pro™ FPGAs. The accompanying reference design files include an example implementation targeting a Virtex-II XC2V3000FF1152 -5 speed grade device.

This application note describes the implementation of Variable Length Coding (VLC) on Xilinx devices. Zig-zag coding and run length coding are done in an MPEG-2 encoder. The zig-zag coding arranges the DCT coefficients in the order of increasing frequency. These coefficients are then coded as a run-length pair where the run is the number of occurrences of a value and the length is the amplitude.

This application note describes the use of partial reconfiguration in Virtex™ series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex SelectMAP interface as well as configuration and readback operations. An in-depth review of Xilinx Application Note XAPP138 is highly recommended.

This application note describes a reference design for a Virtex™-E FPGA interface to an Intel Pentium™ processor. The Pentium I™ system bus, design concerns, and possible applications of this design are discussed. Additionally, the differences between the Pentium I, II, and III busses are discussed. For more information specific to the Intel Pentium family of processors, see the Intel developer web site (http://developer.intel.com/).

CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing requirements for data organization and read/write performance. The innovative design described in this application note is suited for small embedded CAMs with high-speed match and write requirements. The reference design is built using the true Dual-Port block SelectRAM™+ feature of Virtex™ FPGAs. Application Note XAPP201, "An Overview of Multiple CAM Designs in Virtex Devices," discusses the diverse solutions available when implementing CAM while introducing the specific solution described in this application note.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.

This application note describes a reference design for a mixed-version IP router (MIR) servicing up to four gigabit Ethernet ports. MIRs are useful where several gigabit Ethernet networks are operating with a mixture of IPv4 and IPv6 hosts and routers attached directly to the networks, and further nodes reached via the routers. A particular benefit of an approach based on the Virtex-II Pro™ family is that the router’s functions can evolve smoothly, maintaining router performance as the organization migrates from IPv4 to IPv6 internally, and also as the Internet migrates external

This application note provides a quick and simple method for estimating power consumption of CoolRunner-II CPLDs. As an alternative to XPower, power can be quickly and easily computed using the provided equation and coefficients as described in this application note.

This application note describes two reference systems illustrating how to build an embedded PowerPC® 405 system.

This reference system provides a mechanism to access the Ethernet PHY registers.

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

This application note describes a CIO DDR RLDRAM II controller design implemented in a Virtex®-4 device.

This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10 device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines.

This application note covers the principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power distribution system can be designed and verified. The final section discusses additional sources of power supply noise and provides resolutions.

This Application Note discusses the procedures and some commonly asked questions related to the creation of pin placement prior to implementation. The procedures and questions are tailored to several applications of memory interfaces, LVDS interfaces, and other applications.

This application note discusses the fundamental flows of the Pinout Area Constraints Editor (PACE) tool. The PACE tool was created to simplify constraining tasks that are performed relatively early in the design process: I/O Pin assignment and Area Group creation. Widespread PACE usage is anticipated, especially for I/O Pin assignment, as all users must perform this task for every design. Rapidly increasing package sizes and I/O counts make PACE a particularly vital tool.

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This application note describes the implementation and timing details of a four-word burst Quad Data Rate (QDR II) SRAM interface for Virtex®-5 devices.

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

This application note outlines how to successfully configure a Spartan™-3A FPGA from a Platform Flash PROM. Including hardware requirements and software flows for generating and programming PROM files.

Due to rapidly expanding networking industry demands, there is a corresponding need for faster and faster search capabilities within Content Addressable Memory (CAM) devices. Every year new CAM devices emerge on the market. These devices have excellent capabilities and options, but they require an accompanying interface. Virtex™ devices have all the necessary features to interface with high-speed Cams. This document describes a Virtex CAM controller for the Search Engine (a type of CAM device) from Lara Networks.

This application note compares the performance between software and hardware implementations of an LPM algorithm. It shows how the hardware implementation, which uses the APU interface of Virtex®-4 FPGAs, outperforms the software implementations.

This document describes the macrocell configurations of Xilinx® CoolRunner™ XPLA CPLDs.

This application note shows how the 32-bit MicroBlaze™ processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus.

This application note describes a 267 MHz (and above) DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

The application discusses the use of the Xilinx® Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

Using and Creating Flash Files for MicroBlaze™.

This application note describes a system using the Virtex™-5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-5 ML505 development board.

This is a reference system for the OPB Ethernet MAC.

This application note describes a reference design of multi-channel digital up converters(DUCs) and digital down converters (DDCs) for CDMA2000 and UMTS base stations. The provided DSP algorithms meet base station specifications using digital-to-analog conversion rates of 61.44 MHz. Four-channel implementations are described that efficiently map the DSP algorithms into the resources of the Spartan™-3 family of FPGAs.

This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet (TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0.

Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.

Spartan™-XL FPGAs come equipped with a Power Down mode that permits an exceptionally low level of power consumption (ICCO = 100 µA typical), making the family ideal for portable battery-powered applications. This application note provides all the information needed for a designer to use Power Down mode effectively, including descriptions of the mode's common applications, internal functioning and electrical characteristics.

The Virtex™-II SelectLink communications channel utilizes special features of the Virtex-II series of FPGAs, including Digital Clock Managers (DCMs), block SelectRAM+™ memory, and the SelectI/O™ interface, to create a system to move large amounts of data between FPGAs at very high speeds. A code generation tool available at www.xilinx.com allows logic designers everywhere to instantly create customized SelectLink Verilog or VHDL source code.

Quad Data Rate (QDR™Synchronous Static RAM (SRAM) is one of the highest bandwidth solutions available for networking and telecommunications applications. This low-cost, high-performance solution is ideal for applications requiring memory buffering, traffic management, look-up tables, or link lists. This application note describes an implementation of a QDR SRAM controller for Virtex™-II devices using a source synchronous solution.

This application note and reference design provide a digital phase-locked loop (DPLL) solution using minimal external components and spare Virtex™-4 resources. The performance of the DPLL is superior to most integrated mixed-signal solutions. The DPLL design can be used in many different applications, including jitter reduction PLLs, clock multiplier PLLs, clock recovery PLLs, and clock generators.

The non-integer data recovery unit (NI-DRU) presented in this application note is specifically designed for RocketIO™ GTP and GTX transceivers in Virtex®-5 LXT, SXT, TXT, and FXT platforms and consists of look-up tables (LUTs) and flip-flops. The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

This application note documents using a Xilinx® CPLD as a motor controller.

This Application Note describes how to get started using Linux 2.6 and EDK.

This application note demonstrates using a Boundary Scan (JTAG) interface to configure and read back Spartan®-II and Spartan-IIE FPGA devices. Xilinx FPGAs have Boundary Scan features that are compatible with the IEEE Standard 1149.1. This application note is a complement to the configuration section in the Data Sheets and Application Note XAPP176.

This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transceiver of the Virtex-II Pro™ device or an external SERDES with either Virtex-II or Virtex-II Pro devices.

This application note provides implementation guidelines for DDR interfaces using the Digital Clock Manager (DCM) and local inversion clocking techniques for Virtex-II™ Pro devices.

The UltraController™ embedded processor is a complete reference design of a "lightweight" PowerPC™ microcontroler. A 32-bit I/O design is a simple block for integration into larger designs. It only requires a reset and clock input. The UltraController solution utilizes the available PowerPC processor(s) in the Virtex-II Pro™ device and several block RAMs. The UltraController design is available for a variety of applications including logic and data control, device configuration, system monitoring, and simple data manipulation.

This application note describes using asynchronous data capture techniques as a method for high-speed data recovery in Virtex™-II and Virtex-II Pro™ devices. The reference designs accompanying this application note show how data is recovered in an interface running at 622 Mb/s DDR with 0.3UI of jitter.

This document describes an implementation of a low-overhead data synchronization and framing method to use with the LVDS capability of Virtex™-E devices described in XAPP233.

This application note describes how to build a reference system for the PLBv46 PCI Core using the PowerPC™ 405 on the ML410 Embedded Development Platform.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

This document describes the features and benefits of the I/O cells provided by Xilinx® CoolRunner™ XPLA3 CPLDs.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

This application note describes the probability of a metastable event occuring in a Xilinx Virtex™-II Pro FPGA. The test circuit measures the Mean Time Between Failure (MTBF) of these metastable events.

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

This is a reference system for the OPB IIC on the ML402 Evaluation Platform.

This application note describes a low-profile In-System Programming solution, consisting of HDL IP and Xilinx® software tools, designed to handle only the JTAG functions needed for programming; resulting in less logic required and a smaller programming file compared to other full-featured solutions.

This application note describes a 200-MHz DDR SDRAM memory controller implemented in a Virtex™-5 device. This reference design uses the Virtex-5 ChipSync features to calibrate and adjust read data timing. A straightforward backend user interface is provided to allow integration into a complete FPGA design.

For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This document describes several different methods for interfacing 5V signals to CoolRunner™-II devices. These techniques may be used whenever voltage signal levels exceed the maximum input requirements of logic devices.

This application note describes how to use the XC9500™ timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.

The Virtex™-II FPGA series provides dedicated on-chip blocks of 18 Kbit True Dual-Port synchronous RAM for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 to 36 FIFO, with the depth and width being adjustable within the Verilog or VHDL code.

Designed to be implemented in a Virtex™-II FPGA, the Virtex-II SiberBridge is a register transfer logic (RTL) design example demonstrating a reference interface between a 32-bit host (typically a network processor) and the SiberCAM™ device, or a cascade of SiberCAM devices. The SiberCAM device is a large capacity content addressable memory (CAM) product of SiberCore Technologies. The SiberBridge provides a way to initiate searches, obtain search results, and perform table maintenance operations for the SiberCAM, all using a single 32-bit synchronous SRAM or a ZBT SRAM interface. The SiberBridge is intended as a reference design having a low-gate count.

This application note outlines three Galois multiplier solutions of increasing bit-length and complexity, stepping through generation and verification processes.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

This Application Note shows how to use the BDI-2000 Interface.

XC4000/XC5200/Spartan FPGA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This application note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design.

This application note covers the steps necessary to run the open source firmware, Universal Bootloader (U-Boot), and to use it to boot Linux on the embedded IBM PowerPC™ 405 (PPC405) processor available on Virtex-II Pro™ ML300 Evaluation Platforms.

For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This application note discusses different aspects of single-event upsets and recommends appropriate mitigation schemes under each circumstance.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This is the Xilinx® Dual Processor Reference Design suite that accompanies XAPP996 and WP262.

The design described in this application note utilizes the Virtex-II Pro™ RocketIO™ transceivers, the Xilinx Aurora Protocol Engine, and the 1-Gigabit Ethernet MAC core to provide a bridge between Aurora and Gigabit Ethernet. In addition, it can act as a starting point for systems wishing to use either Gigabit Ethernet or Aurora for general data transfer. Target applications include connecting Aurora devices to legacy Gigabit Ethernet networks, testing Aurora devices using Gigabit Ethernet traffic, and building larger systems requiring Aurora or Gigabit Ethernet interfa

This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block(s), you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

This application note describes a 200 MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro™ XC2VP20 FF1152 –6 device.

This application notes describes the CoolRunner™-II CPLD capability called “On the Fly”(OTF) Reconfiguration. OTF permits the CPLD to be operating with a design pattern and simultaneously acquire a second pattern during the operation of the first pattern. The second pattern can be configured into the device with a minimal disturbance to the operation of the device. Additional capabilities, applications and limits to this operation are discussed in further sections.

Frequently, the power voltage applied to a board is higher (or lower) than the nominal 1.8V VCCINT level required by CoolRunner™-II CPLDs. In these situations, power-ICs are commonly used to perform the required DC-to-DC conversion of the power voltage. These devices, known as regulators, take an unregulated input voltage and provide a regulated output voltage independent of input voltage variations or output current fluctuations. Many different types of regulators exist. This application note provides an explanation of each regulator type and presents some typical circuits to highlight currently available commercial regulators.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.

This document provides an overview of Hardware Co-Simulation in System Generator for DSP from a performance perspective, and provides information to help reduce long simulation run times.

Internet Reconfigurable Logic (IRL™) is a system design methodology used to enable the remote upgrade of hardware while insuring the reliability of the upgrade. FPGAs, which are “Field Programmable”, are inherently capable of changing their functionality with a new bitstream. IRL takes advantage of this capability by delivering new bitstreams and software drivers to the remote hardware. This application note describes the basic concepts of an IRL-enabled system, detail design considerations for building an IRL system, and provides a high-level description of PAVE, the Xilinx API and development framework that enables embedded systems to be upgraded.

This is an application note for programming serial Flash memory and the Strata Flash memory for the MicroBlaze™ Development Kit - Spartan®-3A DSP 1800A Starter Platform.

This application note describes how the standard network performance suite NetPerf is used to measure XPS LL TEMAC performance with Wind River VxWorks 6.3.

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

This application note describes a design that reduces latency through the receive elastic buffer of the Virtex™-II Pro RocketIO™ transceiver. This note is applicable only for designs that do not use the clock correction or channel-bonding features of the RocketIO transceiver. (These operations can still be done in the fabric, if needed.)

This application note describes the implementation of a RocketIO™ transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex-II Pro™ FPGA. To build a system, an IBM CoreConnect™ infrastructure connects the PowerPC™405 processor (PPC405) to external memory and other peripherals using the processor local bus (PLB) and device control register (DCR) buses. The reference design uses a two-channel Xilinx bit-error rate tester (XBERT) module for generating and verifying high-speed serial data transmitted and received by the RocketIO transceivers

This application note describes a pre-engineered solution for Virtex-II Pro™ devices using the IBM PowerPC™ 405 core to perform a partial reconfiguration of the RocketIO™ Multi-gigabit Transceivers (MGTs) pre-emphasis and differential swing control attributes. This solution is ideal for applications where these attributes must be modified to optimize the MGT signal transmission for various system environments while leaving the rest of the FPGA design unchanged. The hardware and software elements of this solution can be easily integrated into any Virtex-II Pro design. The associated reference design files provide support for all members of the Virtex-II Pro family.

This application note helps designers get the best results from XC9500XL™ CPLDs. Included are practical details on such topics as pin migration, timing, mixed voltage interfacing, power management, PCB layout, high speed considerations and JTAG best practices.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes how to achieve low-cost serial configuration for Spartan™/Spartan™-XL FPGA designs, including: taking advantage of unused resources in a design (thereby reducing cost), part count, memory size, and board space. The idle processing time of an on-board controller is used to load configuration data from an off-board source, which allows a Spartan design to be upgraded in the field by sending the bitstream over a network.

This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. This note also discusses the functionality of the UART.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan®-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner-II 256-macrocell CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 19 for instructions. This design fits both XPLA3 and CoolRunner-II CPLDs. For the CoolRunner XPLA3 CPLD version, please refer to XAPP333, CoolRunner CPLD I2C Bus Controller Implementation.

This application note discusses the use of the Xilinx Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

This application note presents a design of a port expander that fits into a CoolRunner™-II XC2C32A device. The port expander is SMBus and I2C compatible.

This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern-matching capabilities in the Virtex™-II, Virtex-II Pro™, and Spartan™-3 architectures.

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

This application note describes how to use a Virtex™-5 device to interface to Common I/O(CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices.

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

The Gigabit Ethernet Aggregation reference design (EARD) demonstrates the aggregation of up to eight Gigabit Ethernet ports to SPI-4.2 with optional frame-mapped Generic Framing Procedure (GFP-F).

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Cyclic Redundancy Check (CRC) is an error-checking code widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.

Describes the bahavior of CPLDs during power up.

This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline, and users are encouraged to perform actual studies to optimize the process.

This application note demonstrates how a CoolRunner™-II can be used as a power management device for multiple devices, including Virtex®-II and Spartan®:-3.

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

The Virtex™ FPGA series includes a highly configurable, high-performance SelectIO™ resource to provide support for a wide variety of I/O standards. The SelectIO resource is a robust set of features including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility and SelectIO features and the design considerations described in this document can improve and simplify system level design. Appendix A is a SelectIO update for both the Virtex™-E and Virtex-E Extended Memory (Virtex-EM) product families. Appendix B is the Virtex-E and the Virtex-EM LVDS and LVPECL SelectIO design guide.

The Virtex™ FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system-level design.

This application note describes various methods to configure Spartan™ series FPGAs. Each configuration method is described in detail. Information on necessary software programs to run with input files required, output files produced, download cables used, and other hardware necessary to accomplish the task is discussed. This application note targets users who are new to Xilinx® devices and Alliance/Foundation series software tools and is intended to make the configuration and debugging flows easy to understand.

Power consumption plays an important role in battery-powered applications. Spartan™-XL FPGAs are designed with segmented routing, 3.3-V operation, and advanced process technology to meet the needs for low power and high performance. This application note shows how to reduce power consumption by selectively disabling portions of the design that are not required all the time. This approach is particularly useful for devices that must be operating at all times. This application note discusses different strategies for reducing the supply current incrementally for an operating device.

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

This application note describes a reference design used to bridge one 4-channel Xilinx SPI-4.2 (PL4) Core to four 1-channel SPI-3 (PL3) Link Layer Cores. The design is implemented in a Virtex™-II device.

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.

This application note provides a functional description of Verilog source code for a keypad scanner.

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

Describes the multipliers in the original Spartan™-3 FPGA architecture. For the Spartan-3E/-3A FPGA families, see the Multipliers chapter in User Guide UG331, Spartan-3 Generation FPGA User Guide.

This application note provides a quick and simple method for estimating power consumption of CoolRunner™ XPLA3 CPLDs. As an alternative to XPower, power can be quickly and easily computed using the equation and coefficients provided in this application note.

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

This application note describes the logic to perform basic word alignment and deframing specifically for SONET/SDH systems, where data is being processed at 16-bits or 64-bits per clock cycle.

This application note describes a method for building a ROM firmware image residing in one location of memory and executing from/in another location. The examples given in this application note use the widely available GNU tools targeted for the PowerPC™ processor.

This application note discusses the usage of timing constraints in a Virtex-II Pro™ design with the PowerPC™ 405 (PPC405) processor. The interaction of the timing constraints with the PPC405, Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), and RocketIO™transceiver are described. The interactions are specified by the clock ratio between the busses and the designs processor block. The clock ratios between the PPC405 and PLB, and the PLB to the OPB are also discussed. A reference design is used to show the exact syntax of the timing constraints and Timing Analyzer results.

This application note demonstrates the use of the Multi CHannel (MCH) On Chip Peripheral Bus (OPB) External Memory Controller (EMC) in a MicroBlaze processor system.

This application note describes the use of LVDS signaling for high-performance multi-drop applications with Virtex™ -E FPGAs. Multi-drop LVDS allows many receivers to be driven by one Virtex-E LVDS driver. Simulation results indicate that the reference design described here will operate from DC up to 311 Mbits/s. This application note includes DC specifications, microstrip and layout guidelines.

This application note describes how to implement a Software UART using a few I/O lines of the Xilinx UltraController GPIO interface.

This application note is a reference system for the PLBv46 PCI core.

This paper describes design practices to synthesize high density designs (i.e., over 100,000 gates), composed of large functional blocks, for today's larger Xilinx FPGA devices using the Synopsys FPGA Compiler. The Synopsys FPGA Compiler version 1998.02, Alliance Series 1.5, and the XC4000X family were used in preparing the material for this application note.

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

This application note describes system design techniques using a low power CoolRunner™ CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to offload operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings.

This application note demonstrates the use of the Multi-Channel OPB Synchronous DRAM controller in a MicroBlaze™ processor system.

The Xilinx Flip-Chip BGA package is the latest package offering for Xilinx high-performance FPGA products. Unlike traditional packaging in which the die is attached to the substrate face-up and the connection is made by using wire, the solder-bumped die-in Flip-Chip BGA is flipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the laminate substrate.

This application note describes a high-speed, optimized implementation of a Virtex-II™ pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in VHDL and Verilog.

For the latest version of this application note, see the IBIS chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This application notes shows how to write stimuli in a high level language.

Huffman coding is used to code values statistically according to their probability of occurence. Short code words are assigned to highly probable values and long code words to less probable values. Huffman coding is used in MPEG-2 to further compress the bitstream. This application note describes how Huffman coding is done in MPEG-2 and its implementation.

This application note is offered as complementary text to the configuration section of the Spartan®-II and Spartan-IIE data sheets and provides a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.

The embedded PowerPC™ 405 processor blocks in Virtex-II Pro™ devices with –7 speed grades can achieve speeds to 400 MHz. Special considerations are necessary when using the left processor in dual-processor devices. This application note describes these considerations and provides a necessary macro when operating the left processor at speeds greater than 350 MHz.

Some FPGAs require a minimum supply current in order to power on. For many applications, power supplies selected to cover operating current requirements can readily source enough instantaneous current to satisfy the power-on current requirement. For other applications, there may be a strict limit on the available supply current. The addition of a large capacitor and a few other passive components permit power-on with less supply current than the power-on specification requires. This application note presents a number of these “power-assist” solutions.

FPGAs require a minimum supply current in order to power on. This application note explains the nature of the current, the implications of the power-on current specifications, and the major factors that influence the current. Board-level considerations and regulator selection follow. The last section introduces an approach to FPGA power-on in the presence of an overcurrent protection circuit.

This document details specific implementation techniques which may be used to decrease power consumption in CPLD designs.

This application note demonstrates the use of On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the SMSC LAN 91C111 controller chip in a PowerPC™ 405 processor based reference system.

The Ethernet Cores Hardware Demonstration Platform application note describes the functionality of Ethernet cores in Xilinx FPGA hardware. The development board requirements, setup and MAC core-specific design components are provided, as well as a description of the graphical user interface (GUI) used to control the demonstration platform. The platform demonstrates how to integrate these cores into a system, interface the Ethernet cores to a microprocessor, generate the required clock resources, handle the Ethernet data flow using packet FIFO and flow control, and connect to a physical interface.

Xilinx Alliance software version 3.3.06i (3.1i Service Pack 6) or later has been enhanced to include logical and timing cross-probing to Synplify™/Synplify Pro and LeonardoSpectrum™. The logical cross-probing feature enables the user to select instances or nets in warning or error messages in the Error Viewer to cross-probe back to the synthesis tool schematic view. This is useful for debugging a design with logical DRC errors/warnings. The timing cross-probing feature enables the user to select a path, nets, or instances to cross-probe from the timing report within Timing Analyzer back to the synthesis tool schematic view.

This describes how to use Create IP Wizard to create custom IP and how to then use it in EDK.

This application note describes how to build a reference system using the OPB PCI Core on the ML410.

CPLD design has advanced significantly beyond that of fast PAL design. Today's CPLDs must operate in systems that include microprocessors, memories, I/O devices, buses, multiple power supplies and multiple frequency clocks. The actual logic design is frequently minor with respect to the electrical issues that must be dealt with during debug.

This application note describes how to build a reference system for the PLBv46 PCI using a MicroBlaze based system in the ML555.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

The Spartan-3A/3AN/3A DSP FPGA families offer an advanced static power management feature called Suspend mode, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. The device can quickly enter and exit Suspend mode as required in an application.

This application note discusses a reference design that demonstrates a logic-based, variable speed, three-phase AC induction motor controller.

This application note discusses system and FPGA design techniques for applications that operate in space or in other environments exposed to heavy ion or charged particle radiation. Single Event Upset (SEU) detection, correction, and mitigation for the XQR4000XL are demonstrated.

This is an OPB IIC reference design for the ML403.

This application note describes a method for bypassing the AC coupling in Virtex™-II Pro X devices. Doing so allows use of the 10 Gb/s RocketIO™ Multi-Gigabit Transceiver (MGT) in DC-coupled over-sampling applications.

This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex®-5 and Spartan®-3E FPGA families. The ISE® Design Suite with iMPACT in-system programming solution with Xilinx cables for prototype designs is also described.

This Application Note presents a method for doubling the frequency resolution of counter and timer applications using CoolRunner™-II.

This document describes the CoolRunner™-II timing model. Understanding the CoolRunner-II timing model is essential to creating a CPLD design that meets the desired timing requirements.

This application note describes how to generate statistical profiling information from the IBM PowerPC 405D, which is embedded in some Virtex-II Pro™ FPGAs. Specifically, the application note details how to convert trace output files generated from the Agilent Technologies Trace Port Analyzer into a gprof (GNU profiler) readable format. The gprof tool is capable of generating a histogram of a program's functions and a call-graph table of those functions.

Content Addressable Memory (CAM) or associative memory, is a storage device, which can be addressed by its own contents. Each bit of CAM storage includes comparison logic. A data value input to the CAM is simultaneously compared with all the stored data. The match result is the corresponding address. A CAM operates as a data parallel processor. CAMs can be used to design Asynchronous Transfer Mode (ATM) switches. Implementing CAM in ATM applications is specifically described in this application note. As a reference, the application note XAPP201, “An Overview of Multiple CAM Designs in Virtex Devices,” presents diverse approaches to implement CAM in other designs.

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan™ and Virtex™ FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

This application note describes a parameterizable 8b/10b Encoder and is accompanied by a reference design that replaces the 8b/10b Encoder core, previously delivered through the CORE Generator™ software.

Document provides a discussion of strategies and representative calculations for handling single event upsets (SEUs) with an emphasis on reliability when addressing these low probability events.

This application note discusses the designing of an EDK core with a LocalLink Interface.

This application note targets Virtex™-II Pro designs for which there is a requirement to directly use RocketIO™ transceivers in 16-bit mode. Use this reference design when 8b/10b data encoding is not required and the output frequency needs to be 16 times the system frequency.

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note provides a tutorial which covers the implementation of a simulated AC Induction motor driver; it is intended to serve as a very basic introduction for new users of Project Navigator.

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Xilinx 1-Gigabit Ethernet Media Access Controller Processor Core.

The serial transfer of data between devices on a board or cards on a backplane using the LVDS differential standard is well established. Existing cards need to be able to interface to newer technologies. This application note discusses two possible ways to interconnect standard LVDS transceivers with the Current Mode Logic (CML) technology used in Xilinx RocketIO™ multi-gigabit transceivers (MGTs) through AC coupling and DC coupling.

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

The Constant (k) Coded Programmable State Machine (KCPSM) presented in this application note is a fully embedded 8-bit microcontroller macro for the Virtex™ and Spartan™-II devices. The module is remarkably small at just 35 CLBs, less than half of the smallest Spartan™ XC2S15 device, and virtually free in an XCV2000 device by consuming less than 0.37% of the device CLB.

This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™-II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master. To obtain the VHDL code described in this document, go to section VHDL Code Download and Disclaimer, page 19 for instructions. This design fits XC2C256 CoolRunner-II or XCR3256XL CoolRunner<™ XPLA3 CPLDs. For the CoolRunner-II CPLD version, please refer to XAPP348, CoolRunner™ Serial Peripheral Interface Master.

This application note describes the local clocking resources available in the Virtex-II Pro™ architecture for the RXRECCLK of the 3.125 Gb/s RocketIO™ MGTs.

This application note describes the implementation of a RocketIO X™ bit-error rate tester (XBERT) reference design. The reference design generates and verifies non-encoded high speed serial data on one or multiple point-to-point links (2.5 Gb/s to 10 Gb/s) between RocketIO X multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II Pro X FPGA.

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This reference system demontrates improving system performance in the PowerPC® 440 Processor Block on the Virtex® -5 FXT FPGA.

The Xilinx Spartan™-3A DSP FPGA features the ability to configure from standard serial flash over a built-in Serial Peripheral Interface (SPI). As general-purpose flash, the SPI serial flash can also be used for any other non-volatile storage that you might require. One such non-volatile purpose is the storage of MicroBlaze™ processor application code for bootloading.

This application note describes how to indirectly program select BPI PROMs through the JTAG interface of a Virtex®-5 FPGA using iMPACT. The required hardware setup, BPI-UP PROM file generation, and the indirect programming flow are described.

This application note demonstrates how to use a CoolRunner™-II CPLD as a Level Translator.

Virtex™-E devices provide dedicated on-chip differential receivers between adjacent user I/O pins, which are ideal for receiving LVDS signals at speeds of up to 622 Mb/s in the -7 speed grade. This application note describes how to design a high-speed, low-voltage differential signaling (LVDS) transmitter and receiver in a Virtex-E FPGA suitable for point-to-point data transmission at a data rate of 622 Mb/s.

This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect (PLBv46 PCI) Core using the MicroBlaze™ processor-based embedded system in the Avnet Spartan™-3 Evaluation Board.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML505 Embedded Development Platform.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

This application note describes a 267-MHz DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this number is directly or inversely proportional to the voltage. The analog to digital converter (ADC) described here uses a Virtex™ FPGA, an analog comparator, and a few resistors and capacitors. An 8-bit ADC can be implemented in about 16 Virtex CLBs, and a 10-bit ADC requires about 19 CLBs.

This application note describes a reference system that demonstrates the use of the Multi-CHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate (DDR) Synchronous DRAM (SDRAM) controller in a MicroBlaze™ processor system.

The Spartan™-II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs with programmable interface standards. This application note describes how to take full advantage of the flexibility of the SelectIO features and the design considerations to improve and simplify system-level design.

The Virtex™ FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 x 8 FIFO, with the depth and width being adjustable within the Verilog or VHDL code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade.

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

Describes the hardware accelerator for RAID6 parity generation / data recovery controller with ECC and MIG DDR2 controller.

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

Virtex™-5 devices have a high-precision programmable delay element (IDELAY) associated with every input pin. This application note shows how to implement 8X oversampling of many data streams using a single DCM, two global clock resources, and minimal FPGA logic resources. This solution provides better jitter tolerance than techniques using multiple DCMs. When paired with a suitable data recovery scheme, this oversampling technique can be used with many different data protocols up to 550 Mb/s. A reference design is included that implements a SD-SDI (SMPTE 259M) receiver running at 270 Mb/s.

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The receiver operates at 1:6 deserialization on each of the 16 data channels. Similar to XAPP855, the design also includes a real-time window monitoring circuit for added performance. This reference design calibrates and compensates for skews associated with process, voltage, and temperature (PVT) at initialization and dynamically during operation.

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller(PLB_TEMAC).

Describes the Tri-Mode Ethernet MAC (TEMEC) UltraController-II module, which is a minimal footprint, embedded network processing engine based on the PowerPC™ 405 processor core and the TEMAC core embedded within a Virtex™-4 Platform FPGA.

This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a Virtex™-4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB).

This application note describes the XC4000/Spartan™ Readback capability and its use. Topics include: initialization of the Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back FPGA devices, and Cyclic Redundancy Check (CRC).

This application note is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience. Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design.

This application note provides the necessary steps to get started with the EDK and Tornado 2.2.1/VxWorks 5.5.1 from installation to booting VxWorks on the ML300.

This application note describes a transmitter module and a receiver module compatible with Analog Devices TigerSHARC TS20x digital signal processors (DSPs). These two macros allow double data-rate (DDR) communication of 128-bit words over a four-bit LVDS link at speeds up to 1000 Mb/s per line (500 MB/s) when a Virtex-II™ Pro grade -7 device is transmitting, and up to 500 Mb/s per line when a Virtex-II Pro grade -7 device is receiving.

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for controlling a serial ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD.

This application note describes an embedded Simple Mail Transfer Protocol (SMTP) client reference design that demonstrates the capacity of a network-enabled embedded system to report on its status via E-mail. It describes how to set up the Platform Studio design environment for the PowerPC™ 405, configure the 10/100 Ethernet MAC core, and create the Board Support Package (BSP) for VxWorks®.

Today's serial backplane implementations support line rates ranging from 622 Mbps to 3.125 Gbps and are now approaching speeds in excess of 10 Gbps. A significant recent development is the emergence of standards to define serial backplanes. Whether proprietary or standards-based, serial backplanes present a very demanding signaling environment with high signal density, multiple connectors, and substantial trace lengths. Proving and characterizing the performance of any high-speed serial solution is critical, and MultiBERT provides a means of accomplishing this with Xilinx™ Multi-Gigabit Transceivers (MGTs).

This application note provides a reference system for the PLB PCI on the ML410 Embedded Development Platform.

HyperTransport is a high-speed bus designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. The HyperTransport bus provides this performance enhancement while remaining compatible with PCI. A minimal version of the HyperTransport protocol called HyperTransport Lite has been developed and is described in this application note. The reference design is implemented in a Virtex™-II device and can run at a frequency of up to 400 MHz.

This application note provides a reference design for point-to-point (FPGA to FPGA) high-speed serial packet transfer functionality using the integrated Endpoint block for PCI Express® designs in a Virtex™-5 LXT FPGA.

This reference system tests the operation of the OPB CAN core in loopback mode.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Mixed signal systems require logic parts that can operate with two power supplies. XC9500™ CPLDs are designed to operate in either mixed 5V/3.3V systems or 5V-only systems. To handle both conditions, care has been taken to ensure that designers need not introduce elaborate circuitry to guarantee that 5V and 3.3V power supplies rise or fall in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these CPLDs.

This application note describes the card-side implementation of an 16-bit CompactFlash (CF+)card interface using a CoolRunner™-II CPLD. Included in this implementation are the CIS, Attribute Memory Control and Status Registers, 16-bit Common Memory, and 8-bit I/O Interface. This design can be easily modified to interface to any memory, DSP or microcontroller.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

This application note discusses the use of Wind River VxWorks Real-Time Operating System (RTOS) on a ML507 board.

This application note describes a parameterizable 8b/10b Decoder, and is accompanied by a reference design that replaces the 8b/10b Decoder core, previously delivered through the CORE Generator™ software.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For other device families, see XAPP150.) For additional data, see the Xilinx IBIS files.

TCP/IP is a communication protocol stack designed to provide a reliable data stream between two hosts. It is a popular means of communicating data over a network. Most people use the protocol every day to check email, browse the web, instant message, and download files. TCP/IP is also becoming more utilized in embedded systems. This application note explores the use of an open source TCP/IP stack on the Virtex-II™ Pro PowerPC™ processor. An example reference design is provided allowing remote interaction with the peripherals on the Insight/Memec designed Virtex-II Pro development board.

This application note describes in-circuit partial reconfiguration of RocketIO™ transceiver attributes using the Virtex-II Pro™ internal configuration access port (ICAP). The solution uses a Virtex-II Pro device with an IBM PowerPC™ 405 (PPC405) processor to perform a partial reconfiguration of the RocketIO multi-gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes. These attributes must be modified to optimize the MGT signal transmission prior to and after a system has been deployed in the field. This solution is also ideal for characterization, calibration, and system testing.

Data regeneration is an important function in RAID controllers and is best performed by dedicated hardware under the control of a microprocessor. The Virtex-II Pro™ FPGA can perform both the hardware and software functions required for a RAID parity generator and data regeneration controller. This reference design uses burst mode SYNCBURST™SRAM memory accesses and an internal block SelectRAM+™ memory to provide an extremely efficient hardware design in a Virtex-II Pro FPGA.

An unused RocketIO MGT can be used as a frequency synthesizer, generating a low-jitter clock for use either in the FPGA or in the rest of the system.

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan™-DSP and Virtex™-5 FPGAs.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000™ Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. Emphasis is on the fast, efficient and reliable generation of the handshake signals FULL and EMPTY, which determine design performance.

This application note provides a basic outline for creating a cryptographic processor using CoolRunner™-II devices and a CPLD version of the PicoBlaze™ processor.

This application note utilizes the Virtex-II Pro™ transceivers and the Xilinx Aurora Protocol Engine to provide a multi-ported interface to a shared memory system in a backplane environment. Multiprocessor systems are often encountered in backplane systems, and distributed processing applications require access to a shared memory across a backplane bus. Utilization of a hardware test-and-set lock mechanism, along with a software protocol to test for a semaphore grant prior to accessing the shared memory, guarantees atomic access to the shared memory.

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.

This application note demonstrates the use of the On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the Cypress CY7C67300 USB controller in a PowerPC™ 405 processor based reference system.

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block or blocks, you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

This application note is an overview of the Virtex™ architecture, emphasizing data bit location in the configuration bitstream. Knowing bit locations is the basis for accessing and altering on-chip data. FPGA applications can be built that change or examine the functionality of the operating circuit without stopping the circuit loaded in the device. This application note includes a glossary.

This application note describes three ways to implement the Y'CrCb Color Space to R'G'B' Color Space conversion necessary in many video designs.

The inclusion of embedded processor cores in Xilinx FPGAs opens new doors for high-throughput digital signal processing applications. System Generator for DSP is a high-level modeling environment for designing custom DSP data paths with performance and efficiency comparable to hand-crafted designs. Because System Generator for DSP is tightly integrated with the Simulink® and MATHLAB® tools from The Mathworks, Inc., FPGA designs are implemented by users in a familiar setting without being overly concerned with underlying hardware details.

With the release of M2.1i, Floorplanner supports the Virtex™ family of FPGAs. This application note illustrates how the major Virtex-specific architectural features, such as BlockRAMs, global clock buffers, DLLs, and carry logic, are represented within the Floorplanner GUI and how designers can manipulate a design containing these elements.

This application note presents information on version 2.1i of the FPGA Editor and how it differs from the previous version of EPIC. (For general FPGA Editor usage, refer to the FPGA Editor Guide.) This application note also discusses how to return to EPIC type actions for zoom and pan actions.

The 2.1i software includes improvements in the Trace, Timing Analyzer, FloorPlanner, Constraints Editor, and other implementation tools to help make the designing procedure easier for Virtex™ devices. This paper is devoted to describing some of the simple steps necessary to constrain a Virtex design with the 2.1i implementation tools. The paper explains how to constrain with a CLKDLL in Virtex and examines the new look of the Timing Analyzer Reports.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Triple Module Redundancy (TMR) combined with Single-Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only supported for the Virtex™ series of Xilinx FPGAs. (Xilinx Application Note XAPP216 describes the use of Readback and Partial Configuration for SEU detection and correction.) This application note outlines the recommended design methodology for constructing and implementing TMR logic within the Virtex architecture.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This application note describes the implementation and timing details of a four-word burst QDR II SRAM interface for Virtex®-4 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-4 family to achieve performance levels up to 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s.

This application note provides a detailed description of the Spartan®-3 FPGA family configuration architecture. It explains the composition of the bitstream file and how this bitstream is interpreted by the configuration logic to program the part.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

This application note describes the implementation of Linear Feedback Shift Registers (LFSR) using the SRL macro available in the Virtex™ and Virtex™-II series of FPGAs. The optimal implementations of a 15-bit LFSR, a 52-bit LFSR, and a 118-bit LFSR are also discussed.

This document provides a brief description of how to perform ISP operations with XPLA3 CPLDs.

This application note describes the use of the XC9500XL™ timing model.

This application note discusses how to design and implement a Bus Master Direct Memory Access (DMA) design for the Endpoint Block Plus Wrapper Core for PCI Express® using the Virtex®-5 FPGA Integrated Block for PCI Express.

This application note demonstrates the process required to update a single design revision in a Platform Flash XCFP PROM using an IEEE Std 1149.1 Boundary-Scan (JTAG) Serial Vector Format (SVF) file.

The full throughput of a Virtex™-4 DSP48 slice can be achieved by time-multiplexing two data streams with a double data rate (DDR) technique. Alpha blending is an example of this technique. This application note describes an alpha blending reference design.

This appnote shows how to use a CoolRunner™-II to interface with multiple SD cards.

This application note discusses XC9500XL CPLD power estimation and optimization and provides designers with an understanding of sense-amplifier-based CPLD power dissipation. The note also provides a brief discussion of the process for estimation. With this information, you can accurately assess the power dissipation for a design. Guidelines that permit you to make key choices to manage the power dissipation of your design and understand the package thermal limits are also presented.

Designing high-speed memory interfaces is a challenging task. Xilinx makes it simple to design such interfaces using the Virtex-II™ and Virtex-II Pro™ FPGAs. This application note discusses the challenges presented by this task, together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. All examples used in this application note assume a DDR-1 interface on an XC2VP20FF1152-6 Virtex-II Pro FPGA. The interface speed is 200 MH.

This application note discusses the enormous strides made by Spartan™ series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement. The Spartan device family offers many of the features that are desired by Gate Array designers with the major advantage of programmability, which can prove to be the key factor in the success of the product.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes XC4000XL/XLA and Spartan™-XL I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. However, such parameters are not production-tested and are, therefore, not guaranteed.

Content Addressable Memory (CAM) offers increased data search speed. In various applications based on CAM, there are differing requirements for data organizations and read/write performance. The innovative design described in this application note is suited for small embedded CAMs with high-speed match and write requirements. The reference design is built using the true dual-port block SelectRAM+™ feature for the Virtex™-II series, including the Virtex-II Pro™ devices.

This application note defines timing parameters required for the timing analysis of source synchronous and system synchronous applications. The parameters discussed in this application note are listed in Module 3 of the Virtex™-II and Virtex-II Pro™ data sheets. This application note explains the DCM clock phase accuracy parameters, system-synchronous pin-to-pin setup/hold with DCM parameters (TPSDCM and TPHDCM), and all source-synchronous parameters. Memory interfaces and the XGMII interface analyses are provided as examples

Implementation of a simple temperature controller in a CoolRunner™-II device.

This 10-Gigabit Ethernet Hardware Demonstration Platform application note describes the functionality of the LogiCORE™10-Gigabit Ethernet and XAUI cores in Xilinx® FPGA hardware. It includes development board requirements, setup instructions, MAC core-specific design components, and a description of the graphical user interface used to control the demonstration platform.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

The Xilinx Mesh Fabric Reference Design is a development vehicle for full mesh line cards based on Virtex™-II Pro devices. The design is a fully parameterized IP component that lets designers partition a mesh fabric design into any combination of Virtex-II Pro devices.

This application note and its accompanying reference design describe a dynamic phase alignment (DPA) module used in bus interfaces, such as SPI 4.2, using asynchronous data capture techniques. The DPA module can run at 800 Mbps and faster in Virtex-II™ and Virtex-II Pro™ devices. It contains a word-alignment unit that can remove channel-to-channel skew. This document is an extension of XAPP671: High-Speed Data Recovery Using Asynchronous Data Capture Techniques.

The block memories in the Virtex™-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

This application note addresses low-cost, four- to six-layer, high-volume printed circuit board (PCB) layout for a Spartan™-3E FPGA in the FT256 1 mm BGA package. Intended for design engineers, managers, and PCB layout staff, who are already familiar with SI related design issues. The general guidelines can be used to optimize board layout for other devices and packages.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This Virtex™-5 application note describes an SFI-4.1 interface, a 16-channel, source-synchronous LVDS interface operating at SDR. The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input.The timing of the receiver is described in depth and characterized in hardware.

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The design takes advantage of the Virtex™-5 I/O ChipSync™ features ability to adjust the delay of the receiver datapaths creating dynamic setup/hold timing for each device at initialization, compensating for skews associated with the manufacturing process. The receiver operates at 1:8 deserialization on each of the 16 data channels.

This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.

This application note shows how a Xilinx Virtex-II™ or Virtex-II Pro™ device can connect to a Philips TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver. The reference design with this application note uses the TZA3015HW.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This application note describes methods which will produce consistently fast designs when used with Xilinx® CoolRunner™-II CPLD family. More detail on this important new family of 1.8V CPLDs is available at the Xilinx Web site (www.xilinx.com), where the family and individual part data sheets can be found. Additional application literature is also available. Of particular interest is XAPP375, which discusses the timing of the CoolRunner-II CPLDs, and XAPP376, which discusses the basic operation of the macrocell and function block—the “logic engine” of the CoolRunner-II family.

This application note describes how to implement the CoolRunner™-II advanced features in the Xilinx software. These features include the DualEDGE triggered registers, clock divider, CoolCLOCK, DataGATE, Schmitt trigger inputs, and I/O termination types.

CoolRunner™-II RealDigital CPLDs are the only CPLDs to combine both high performance and low power to form the next generation CPLD. This application note describes the design methodologies that can be employed to obtain the lowest power possible using the CoolRunner-II CPLD by utilizing its unique power saving features.

CoolRunner™-II is the Xilinx® CPLD Family that raises the standard for Complex Programmable Logic Devices. CoolRunner-II delivers unmatched performance with the industry’s lowest power at highly competitive price points in an aggressive spectrum of packages. This application note details how CoolRunner-II CPLDs create logic within their CMOS fabric. In all likelihood, you will never need to know these details as the design software will automatically complete your design giving highest speed and lowest power with very little user direction. In the event that you would like to understand the inside details of how CoolRunner-II does its magic, this application note should help serve that need. For general CoolRunner-II information, also refer to the CoolRunner-II Family Data Sheet and individual device data sheets.

This application note details an embedded system example design of a web server running on a PowerPC™ core within a Xilinx Virtex™-4 FPGA. The system is designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the PowerPC processor.

This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.

This application note describes an alternative method for specifying Relatively Placed Macros (RPMs) using a new grid system called the "RPM Grid." This grid system can be used in the Virtex™-II architectures, including Virtex-II Pro™ devices. This is not a tutorial on how to create RPMs, and this document assumes some knowledge of how to create RPMs. (Please see the Xilinx Libraries Guide for details on capturing RPMs.) This application note describes how to use the RPM Grid to create a heterogeneous relocatable RPM macro containing both block RAM and slice components and demonstrates how this feature can be used to optimize the timing of paths from block RAM outputs to slice registers.

The use of the internal IOB 3-state control register can significantly improve output enable and disable time. This application note illustrates the use of hard macros to implement this register in both HDL and schematic-based designs.

Discovering electrical problems during the debug stage is too late. The printed circuit board has been built and may need significant changes to debug. The best approach is to avoid problems by planning for options at the outset. This application note provides a framework for checklisting a design early to eliminate problems.

This application note contains additional information that may be of use when designing with XC4000™ Series devices. This information supplements the product descriptions and specifications, and is provided for guidance only.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

This application note explains the techniques to support SATA initialization in the GTP transceiver of the Virtex®-5 LXT platform.