2. Technology

20nm UltraScale Devices

Doing More for Less

AMD is multiplying the value of 20nm with the UltraScale architecture and associated family of FPGAs and 3D ICs. Whether viewed from almost every attribute at the chip level or viewed when integrating multiple chips into one or fewer chips at the system level, designers will find compelling value metrics as they migrate from 28nm to 20nm devices.

 

Packet Processing

UltraScale architecture delivers 3X higher system performance and integration for next generation packet processing and transport applications.

 

 

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Waveform Processing

UltraScale architecture delivers TeraMACs of DSP performance in a cost-optimized footprint that requires only half the power and area to address next-generation waveform-processing applications. 

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Image and Video Processing

UltraScale architecture delivers another 2X system performance and integration for next-generation 8K and 4K video processing applications.

 

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High Performance Computing

UltraScale architecture delivers 2X higher system performance and 35% reduction in power for next-generation high performance computing applications.

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Migration Path Benefits

The table below shows the potential chip and system level value multipliers associated with 3 different migration paths.

Migration Path Device Migration System Integration
  • 2.5-4X System Logic Cell Throughput*/$
  • 2-4X DSP Bandwidth/$
  • 1.5-3X Serial Bandwidth/$
  • 2X DDR Memory Bandwidth/$
  • 25-45% Lower Power at Same Performance
  • Up to 3.5X System Performance/$
  • Up to 2X Greater System Performance/Watt
  • Up to 40% System Power Reduction
  • Up to 60% BOM Cost Reduction
 
  • 20-35% Greater System Logic Cell Throughput*/$
  • 25-120% Greater DSP Bandwidth/$
  • 1.5-2X Greater Serial Bandwidth/$
  • 2-4X DDR Memory Bandwidth/$
  • 25-45% Lower Power at Same Performance
  • Up to 2.5X System Performance/$
  • Up to 2.5X Greater System Performance/Watt
  • Up to 50% System Power Reduction
  • Up to 60% BOM Cost Reduction
 
  • 25-50%  Greater System Logic Cell Throughput*/$
  • 10-30% Greater Serial Bandwidth/$
  • 25-45% Lower Power at Same Performance
  • Up to 33% Smaller Devices Through
     Integrated Blocks
  • Up to 3X System Performance/$
  • Up to 2.5X Greater System Performance/Watt
  • Up to 50% System Power Reduction
  • Up to 50% BOM Cost Reduction
  • 28G-LR Drives 2X Port Density/$
UltraScale architecture and Vivado™ Design Suite are co-optimized to enable a device utilization target of 90%, which can result in up to a 30% effective cost advantage relative to the nearest competitor.
*System Logic Cell throughput=logic capacity x average realizable speed of the logic cells

Applications that migrate from Virtex 7 to Virtex UltraScale FPGAs will typically leverage the full capacity of UltraScale devices for programmable systems integration, and the ability to double system level performance, reduce power and BOM cost by up to 50%, while still enjoying significant chip-level value enhancements.

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