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Zynq UltraScale+ RFSoCs

Integrating a Comprehensive RF Analog-to-Digital Signal Chain

Zynq® UltraScale+™ RFSoCs integrate multi-giga-sample RF data converters and soft-decision forward error correction (SD-FEC) into a SoC architecture. Complete with an ARM® Cortex™-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwidth in a Zynq UltraScale+ device, the new family provides a comprehensive RF signal chain for wireless, cable access, test & measurement, early warning / radar, and other high performance RF applications.

Block Diagram Description

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Featuring 8x8 Channel RF-Analog

  • 8x 4GSPS 12-bit ADCs
  • 8x 6.4GSPS 14-bit DACs


Remote Radio for M-MIMO

Mobile/Chip Tester

Test & Measurement Instrumentation

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Featuring Integrated SD-FEC Cores

  • Over 42 Gb/s LDPC Encode System Throughput
  • Over 10Gb/s LDPC Decode System Throughput
  • Over 7Gb/s Turbo Decode System Throughput
  • Support for custom LDPC Code Construction
5G Baseband

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Featuring 8x8 RF-Analog and Integrated SD-FEC Cores

  • 8x 4GSPS 12-bit ADCs
  • 8x 6.4GSPS 14-bit DACs
  • Over 42 Gb/s LDPC FEC Encode System Throughput
  • 10Gb/s LDPC FEC Decode Throughput
  • Support for custom LDPC Code Construction
  • Over 7 Gb/s Turbo Decode System Throughput

Cable Access Remote-PHY

Wireless Backhaul

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Featuring 16x16 Channel RF-Analog 

  • 16x 2GSPS 12-bit ADCs
  • 16x 6.4GSPS 14-bit DACs

Remote Radio for M-MIMO

Phased Array EW / Radar

Value Features
System Performance and Throughput
  • Eliminates discrete ADCs and DACs for reduced footprint
  • Scalable growth path for increasing RF channel-count 
  • Integrated SD-FEC integrated cores 
Unmatched Integration, Performance, and Power
  • Reduces power by removing ADC/DAC components
  • Eliminates FPGA-to-Analog interface power
  • Meets stringent 5G & DOCSIS3.1 LDPC FEC thermal requirements
  • 80% more power efficient SD-FEC  vs. a soft implementation
Proven Productivity
  • RF-design in the digital domain for greater flexibility
  • Eliminates difficult JESD204B/C analog interface design
  • Simplified system and PCB design with fewer components
  • Unified control for digital beamforming & signal conditioning

Direct-RF Signal Chain Features

12-bit, 4.096GSPS ADC - 8 8 8 -
12-bit, 2.058GSPS ADC - - - - 16
14-bit, 6.554GSPS DAC - 8 8 8 16
SD-FEC 8 - - 8 -
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Programmable Logic Features

System Logic Cells (K) 930 678 930 930 930
DSP Slices 4,272 3,145 4,272 4,272 4,272
Memory (Mb) 60.5 41.3 60.5 60.5 60.5
33G Transceivers 16 8 16 16 16
Maximum I/O Pins 241 371 371 371 456
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Processing System Features

Application Processing Unit Quad-core ARM Cortex-A53 MPCore up to 1.5GHz
Real-Time Processing Unit Dual-core ARM Cortex-R5 MPCore up to 533MHz
Dynamic Memory Interface DDR4, LPDDR4, DDR3, DDR3L, LPDDR3
High-Speed Peripherals PCIe® Gen2, USB3.0, SATA 3.1, DisplayPort, Gigabit Ethernet


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Developer Zone

Xilinx offers a comprehensive tool flow for radio design and verification, encompassing logic design, embedded SW development, and simulation. The tool flow ranges from IP and software drivers for RF sampling, to design-entry solutions using C/C++, MATLAB, or Simulink.  The comprehensive development flow increases accessibility at the hardware, software, and system level.

Xilinx's software development environments and embedded platforms offer a comprehensive set of familiar and powerful tools, libraries and methodologies.
Acceleration Zone
Xilinx UltraScale™ and UltraScale+ FPGAs are empowering hardware and application developers in many of the world’s largest and most innovative cloud computing services.
Xilinx devices take conventional programmable logic to an era of integrated programmable systems to capitalize on the benefit of System Integration.
Xilinx provides machine learning solutions including the development stacks and hardware platforms for deploying advanced and efficient neural networks, algorithms and applications.
Xilinx works closely with world class partners like The Mathworks™ and National Instruments™ to enable rapid system development with unrivaled levels of system performance.

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