ISE Foundation Software
Documentation
Related Information
ISE Foundation includes Xilinx SmartCompile technology; an industry-unique combination of capabilities to solve designers' number one design challenge - timing closure.
ISE® Foundation™ software integrates everything you need in a complete logic design environment for all leading Xilinx FPGA and CPLD products. Easy-to-use, built-in tools and wizards make I/O assignment, power analysis, timing-driven design closure, and HDL simulation quick and intuitive.
ISE Foundation also includes PlanAhead™ Lite, a subset of the award winning PlanAhead Design and Analysis Tools to provide I/O pin planning capabilities, design analysis, floorplanning, as well as convenient implementation control.
Device Family Support
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System Requirements
- Microsoft Windows XP Professional (32 and 64 bit)
- Microsoft Windows Vista Business (32 and 64 bit)
- Red Hat Enterprise Linux WS 4 (32 and 64 bit)
- Red Hat Enterprise Linux Desktop 5 (32 and 64 bit)
- SUSE Linux Enterprise 10* (32 and 64 bit)
*SUSE Linux Enterprise 10 Desktop (SLED) and Server (SLES) products are binary compatible.
Key Features
- PlanAhead Lite including PinAhead technology for easy FPGA pin assignmnent and powerful floorplanning capabilities
- New SmartExplorer (Linux only) allowing multiple implementation runs in parallel on multiple machines to better leverage computing resources for more turns-per-day
- Goal-based Implementation allowing users to easily control implementation options based on design goals such as power reduction, area optimization, runtime reduction, or timing performance
- Xilinx SmartCompile™ technology providing a powerful design closure environment
- An integrated timing closure environment to help identify bottlenecks in your Virtex-5 FPGA designs quickly and easily
- With a speed-grade or more in cost savings delivering the lowest total cost in logic design
- Powered by Xilinx Fmax technology to deliver the industry's fastest logic performance