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Xilinx provides a comprehensive TÜV SUD certified design flow solution for our customers to simplify and accelerate certifications based on functional safety specifications across Aerospace & Defense, Automotive, Medical and Industrial markets where safety and reliability are key.

Functional Safety Standards Supported

Application Standard
Automotive ISO 26262
Industrial and Medical IEC 61508, IEC 62061 and IEC 13849
Aerospace & Defense
DO-254/DO178b

Xilinx Unique Value Proposition

Xilinx has decades of proven success and experience across a wide variety of mission-critical industries and applications. Our customers choose our portfolio of FPGAs and SoCs for to enable:

  • Configurability and increased performance at lower power
  • Integration of complex and complete systems into a single device
  • Reliability and long product life time
  • Faster time to market

Certified Hardware and Software Design Tools

  • Design and verification tools certified for use in Functional Safety applications
  • Certified Compiler tools
  • Functional Safety Certificate and Reports
  • Functional Safety Package

Certified Methodologies & IPs

  • Certified functional safety design methodologies enable integration of safety  and non-safety functions in the same device
  • Isolation Design Flow (IDF) and Vivado Isolation Verifier (VIV) / Isolation Verification Tools (IVT) provide a certified methodology to separate areas on a single device. Designs placed into these regions are physically isolated. The areas can be changed at any time without impacting other isolated regions, proven by the VIV/IVT tools (impact analysis)
  • Certified Soft Error Mitigation (SEM) IP cores perform Single Event Upset (SEU) detection, correction, and classification for configuration memory. The cores utilize device primitives such as ICAP and FRAME_ECC to clock and observe the Readback CRC feature as part of the SEU detection function. For SEU correction,  the IP cores perform the necessary operations to locate and correct errors. For SEU classification, the IP cores use Xilinx Essential Bits technology to further increase system availability.

Assessed Safety Concept Design

The Zynq®-7000 All Programmable SoC has been reviewed and assessed for on-chip redundancy by TuV Rheinland. This Safety Concept Design study states Xilinx technology can be used to create a single chip solution that will support 2 independent safety channels for SIL3 safety functions referencing IEC61508 Part2 Annex-E.

Functional Safety Lounge

The Functional Safety Lounge provides access to solutions, documentation and additional resources to subscribers.

To gain access, register or log in.

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.

software-tile
Xilinx's software development environments and embedded platforms offer a comprehensive set of familiar and powerful tools, libraries and methodologies.
Acceleration Zone
Xilinx UltraScale™ and UltraScale+ FPGAs are empowering hardware and application developers in many of the world’s largest and most innovative cloud computing services.
hardware-tile
Xilinx All Programmable devices take conventional programmable logic to an era of integrated programmable systems to capitalize on the benefit of System Integration.
revision-tile
Xilinx provides machine learning solutions including the development stacks and hardware platforms for deploying advanced and efficient neural networks, algorithms and applications.
system-tile
Xilinx works closely with world class partners like The Mathworks™ and National Instruments™ to enable rapid system development with unrivaled levels of system performance.
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